GPIO Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	305.334us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.670s	208.013us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.600s	110.606us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.430s	1.016ms	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	30.314us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	25.814us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.380s	257.696us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	39.888us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.590s	32.058us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	25.814us	20	20	100.00
		gpio_csr_aliasing	0.850s	39.888us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	68.542us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	275.969us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	158.525us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.580s	380.766us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.750s	440.695us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.940s	96.898us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.600s	5.412ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.150s	2.134ms	50	50	100.00
V2	full_random	gpio_full_random	1.120s	115.938us	50	50	100.00
V2	stress_all	gpio_stress_all	4.078m	32.986ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	26.155us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	33.326us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.440s	275.738us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.440s	275.738us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	25.814us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	77.987us	20	20	100.00
		gpio_csr_aliasing	0.850s	39.888us	5	5	100.00
		gpio_csr_hw_reset	0.670s	30.314us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	25.814us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	77.987us	20	20	100.00
		gpio_csr_aliasing	0.850s	39.888us	5	5	100.00
		gpio_csr_hw_reset	0.670s	30.314us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.490s	857.771us	20	20	100.00
		gpio_sec_cm	1.090s	707.968us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.490s	857.771us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.756m	191.243ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 0.gpio_stress_all_with_rand_reset.46077963304420922643345971138950880779990367854092826520088575651589410298406
      Line 6947, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21758495220 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21758495220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.4955106895868426697560149957477064905411578972428314836565588775882063078097
      Line 335, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 764958366 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 764958366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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