GPIO Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	109.907us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	79.808us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.560s	82.325us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	285.759us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	21.367us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	15.741us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.510s	265.406us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	21.479us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.570s	33.021us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	15.741us	20	20	100.00
		gpio_csr_aliasing	0.840s	21.479us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	336.887us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.350s	60.998us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	86.209us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.490s	79.686us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.800s	119.611us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.830s	656.851us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.990s	537.632us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.040s	734.643us	50	50	100.00
V2	full_random	gpio_full_random	1.170s	355.615us	50	50	100.00
V2	stress_all	gpio_stress_all	3.759m	31.647ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	12.691us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	11.887us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.990s	463.663us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.990s	463.663us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	15.741us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	44.859us	20	20	100.00
		gpio_csr_aliasing	0.840s	21.479us	5	5	100.00
		gpio_csr_hw_reset	0.660s	21.367us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	15.741us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	44.859us	20	20	100.00
		gpio_csr_aliasing	0.840s	21.479us	5	5	100.00
		gpio_csr_hw_reset	0.660s	21.367us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	475.619us	20	20	100.00
		gpio_sec_cm	0.930s	340.629us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	475.619us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.319m	196.906ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 0.gpio_stress_all_with_rand_reset.58397989535997918373826010898361709018213938439384065417339352484598993046491
      Line 9262, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38122845233 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38122845233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.36880062509928604121987073837918697880418918280563344539426697112809927667697
      Line 3728, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 128920314901 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 128920314901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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