GPIO Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.430s	75.570us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.550s	363.590us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.630s	110.698us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.590s	127.747us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	36.122us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	15.595us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.350s	3.595ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	16.922us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.430s	106.923us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	15.595us	20	20	100.00
		gpio_csr_aliasing	0.840s	16.922us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	303.482us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.420s	63.109us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.030s	88.905us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.660s	1.111ms	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.820s	575.560us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.780s	354.451us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.710s	1.631ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.930s	2.871ms	50	50	100.00
V2	full_random	gpio_full_random	1.110s	96.618us	50	50	100.00
V2	stress_all	gpio_stress_all	3.974m	37.804ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	12.425us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	170.764us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.990s	135.261us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.990s	135.261us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	15.595us	20	20	100.00
		gpio_same_csr_outstanding	0.980s	175.401us	20	20	100.00
		gpio_csr_aliasing	0.840s	16.922us	5	5	100.00
		gpio_csr_hw_reset	0.680s	36.122us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	15.595us	20	20	100.00
		gpio_same_csr_outstanding	0.980s	175.401us	20	20	100.00
		gpio_csr_aliasing	0.840s	16.922us	5	5	100.00
		gpio_csr_hw_reset	0.680s	36.122us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	445.331us	20	20	100.00
		gpio_sec_cm	0.970s	436.906us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	445.331us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.864m	108.638ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			948	970	97.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test gpio_stress_all_with_rand_reset has 22 failures.

    • 4.gpio_stress_all_with_rand_reset.111930957492801063325016912546876009636721836851886231520196375632825670046624
      Line 1810, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7202795439 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7202795439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.gpio_stress_all_with_rand_reset.82249920614182270584610565858238503538700550439414998723018734282040516824854
      Line 2941, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/5.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28012273920 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28012273920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

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