GPIO Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.520s	441.212us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	117.607us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.440s	102.147us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.430s	344.719us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	18.238us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	44.235us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.580s	2.631ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	59.769us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.640s	61.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	44.235us	20	20	100.00
		gpio_csr_aliasing	0.890s	59.769us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	586.090us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.420s	75.111us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	44.446us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.490s	452.082us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.010s	230.817us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.930s	96.343us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.950s	825.966us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.860s	558.555us	50	50	100.00
V2	full_random	gpio_full_random	1.170s	76.807us	50	50	100.00
V2	stress_all	gpio_stress_all	4.543m	27.124ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	21.853us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	40.311us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.350s	610.408us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.350s	610.408us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	44.235us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	73.647us	20	20	100.00
		gpio_csr_aliasing	0.890s	59.769us	5	5	100.00
		gpio_csr_hw_reset	0.690s	18.238us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	44.235us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	73.647us	20	20	100.00
		gpio_csr_aliasing	0.890s	59.769us	5	5	100.00
		gpio_csr_hw_reset	0.690s	18.238us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	209.876us	20	20	100.00
		gpio_sec_cm	1.000s	398.582us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	209.876us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	51.609m	174.621ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 2.gpio_stress_all_with_rand_reset.68905040839779783829263937568451019090522415317844935294329506063615020867151
      Line 7110, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 155150365067 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 155150365067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.73479346574325085938266993663312608384213496815359448011965468049642860015771
      Line 3517, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70973253260 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 70973253260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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