GPIO Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	74.309us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.600s	105.815us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.580s	420.030us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.570s	82.166us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	218.666us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.710s	48.337us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.400s	764.731us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	58.170us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.500s	38.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.710s	48.337us	20	20	100.00
		gpio_csr_aliasing	0.850s	58.170us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.390s	83.076us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.410s	58.482us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	188.864us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.620s	358.621us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.690s	127.468us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.950s	96.554us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.000s	780.872us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.550s	572.475us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	553.249us	50	50	100.00
V2	stress_all	gpio_stress_all	3.909m	8.454ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.610s	24.713us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	15.481us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.050s	587.061us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.050s	587.061us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.710s	48.337us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	36.996us	20	20	100.00
		gpio_csr_aliasing	0.850s	58.170us	5	5	100.00
		gpio_csr_hw_reset	0.660s	218.666us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.710s	48.337us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	36.996us	20	20	100.00
		gpio_csr_aliasing	0.850s	58.170us	5	5	100.00
		gpio_csr_hw_reset	0.660s	218.666us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	238.765us	20	20	100.00
		gpio_sec_cm	1.040s	679.301us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	238.765us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	44.559m	662.320ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test gpio_stress_all_with_rand_reset has 24 failures.

    • 0.gpio_stress_all_with_rand_reset.23922235791091437438238948420934787573273588357019631105583814080238242002824
      Line 7159, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 283596702894 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 283596702894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.109079126973025422147052463033505685267319014192901279759769063884691514651144
      Line 3227, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29258967525 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29258967525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

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