GPIO Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.460s	345.652us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	517.202us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.600s	77.805us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.480s	177.823us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.640s	41.441us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	112.228us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.320s	1.180ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	74.476us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.930s	313.866us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	112.228us	20	20	100.00
		gpio_csr_aliasing	0.890s	74.476us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	71.863us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.290s	285.954us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.900s	91.689us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.450s	384.465us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.230s	372.758us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.620s	180.338us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.790s	2.113ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.330s	1.219ms	50	50	100.00
V2	full_random	gpio_full_random	1.100s	1.263ms	50	50	100.00
V2	stress_all	gpio_stress_all	3.633m	70.118ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	12.408us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	29.847us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.480s	171.556us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.480s	171.556us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	112.228us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	42.592us	20	20	100.00
		gpio_csr_aliasing	0.890s	74.476us	5	5	100.00
		gpio_csr_hw_reset	0.640s	41.441us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	112.228us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	42.592us	20	20	100.00
		gpio_csr_aliasing	0.890s	74.476us	5	5	100.00
		gpio_csr_hw_reset	0.640s	41.441us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.520s	119.832us	20	20	100.00
		gpio_sec_cm	0.930s	83.946us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.520s	119.832us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.832m	123.819ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test gpio_stress_all_with_rand_reset has 31 failures.

    • 0.gpio_stress_all_with_rand_reset.113601006297338541237983659653637338302961420250225966439791156425469155590559
      Line 5646, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39921687169 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 39921687169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.51305816514263040613573812267462585810354184573628507141884876111553557588916
      Line 2768, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53346391647 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 53346391647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

Past Results

• Latest
• lint
• 2024.06.11_11.45.35
• 2024.06.10_06.30.51
• 2024.06.08_12.58.00
• 2024.06.07_04.41.15
• 2024.06.06_10.52.01
• 2024.06.05_03.42.35