548a3880d8
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | gpio_smoke | 1.560s | 96.905us | 50 | 50 | 100.00 |
gpio_smoke_no_pullup_pulldown | 1.530s | 353.556us | 50 | 50 | 100.00 | ||
gpio_smoke_en_cdc_prim | 1.630s | 373.064us | 50 | 50 | 100.00 | ||
gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.390s | 296.293us | 50 | 50 | 100.00 | ||
V1 | csr_hw_reset | gpio_csr_hw_reset | 0.670s | 16.497us | 5 | 5 | 100.00 |
V1 | csr_rw | gpio_csr_rw | 0.680s | 59.527us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | gpio_csr_bit_bash | 3.130s | 159.855us | 5 | 5 | 100.00 |
V1 | csr_aliasing | gpio_csr_aliasing | 0.780s | 30.670us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.830s | 142.695us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.680s | 59.527us | 20 | 20 | 100.00 |
gpio_csr_aliasing | 0.780s | 30.670us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 255 | 255 | 100.00 | |||
V2 | direct_and_masked_out | gpio_random_dout_din | 1.440s | 296.960us | 50 | 50 | 100.00 |
gpio_random_dout_din_no_pullup_pulldown | 1.400s | 138.442us | 50 | 50 | 100.00 | ||
V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 1.070s | 67.991us | 50 | 50 | 100.00 |
V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.510s | 400.002us | 50 | 50 | 100.00 |
V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.610s | 576.975us | 50 | 50 | 100.00 |
V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 4.010s | 416.457us | 50 | 50 | 100.00 |
V2 | noise_filter_stress | gpio_filter_stress | 28.540s | 1.796ms | 50 | 50 | 100.00 |
V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 7.100s | 2.170ms | 50 | 50 | 100.00 |
V2 | full_random | gpio_full_random | 1.160s | 343.212us | 50 | 50 | 100.00 |
V2 | stress_all | gpio_stress_all | 3.996m | 17.648ms | 50 | 50 | 100.00 |
V2 | alert_test | gpio_alert_test | 0.630s | 16.595us | 50 | 50 | 100.00 |
V2 | intr_test | gpio_intr_test | 0.670s | 12.257us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | gpio_tl_errors | 2.930s | 126.489us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | gpio_tl_errors | 2.930s | 126.489us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | gpio_csr_rw | 0.680s | 59.527us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.910s | 19.207us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.780s | 30.670us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.670s | 16.497us | 5 | 5 | 100.00 | ||
V2 | tl_d_partial_access | gpio_csr_rw | 0.680s | 59.527us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.910s | 19.207us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.780s | 30.670us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.670s | 16.497us | 5 | 5 | 100.00 | ||
V2 | TOTAL | 640 | 640 | 100.00 | |||
V2S | tl_intg_err | gpio_tl_intg_err | 1.540s | 172.739us | 20 | 20 | 100.00 |
gpio_sec_cm | 0.960s | 95.583us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.540s | 172.739us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 41.840m | 1.881s | 18 | 50 | 36.00 |
V3 | TOTAL | 18 | 50 | 36.00 | |||
TOTAL | 938 | 970 | 96.70 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 14 | 14 | 14 | 100.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.63 | 99.06 | 99.24 | 100.00 | -- | 99.80 | 99.68 | 99.99 |
UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 32 failures:
0.gpio_stress_all_with_rand_reset.43337823769594293166397478555280423134922365481673865887276022576878489215039
Line 4955, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 79321068889 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 79321068889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.gpio_stress_all_with_rand_reset.77037429296453099471199946157214245305660266894000952501971274109972621988069
Line 757, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2464535748 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2464535748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.