GPIO Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	312.138us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.700s	156.069us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.540s	95.919us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.570s	194.664us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	35.993us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	44.259us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.210s	264.297us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.810s	18.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.890s	39.227us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	44.259us	20	20	100.00
		gpio_csr_aliasing	0.810s	18.354us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.490s	37.216us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.530s	511.032us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.050s	30.899us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	168.422us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.820s	428.347us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.750s	311.922us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.500s	1.269ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.480s	632.622us	50	50	100.00
V2	full_random	gpio_full_random	1.170s	411.336us	50	50	100.00
V2	stress_all	gpio_stress_all	3.999m	19.281ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	69.472us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	79.777us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.950s	321.011us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.950s	321.011us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	44.259us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	146.311us	20	20	100.00
		gpio_csr_aliasing	0.810s	18.354us	5	5	100.00
		gpio_csr_hw_reset	0.650s	35.993us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	44.259us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	146.311us	20	20	100.00
		gpio_csr_aliasing	0.810s	18.354us	5	5	100.00
		gpio_csr_hw_reset	0.650s	35.993us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	462.835us	20	20	100.00
		gpio_sec_cm	1.000s	330.752us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	462.835us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	44.028m	115.436ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 0.gpio_stress_all_with_rand_reset.11000964194686728593130333439364158207187114354397542510112666001938584880148
      Line 24147, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 544664847688 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 544664847688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.87150101140558776100878657925884320760070411851175519653274694503801267769830
      Line 1594, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5897542851 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5897542851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

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