GPIO Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	381.451us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	376.141us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.490s	323.224us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.410s	94.745us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	15.369us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	46.968us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.350s	714.658us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	31.608us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.520s	135.853us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	46.968us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.608us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.440s	269.533us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	52.142us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	78.107us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.380s	146.766us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	236.929us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.910s	89.484us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.000s	3.907ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.030s	4.133ms	50	50	100.00
V2	full_random	gpio_full_random	1.240s	97.606us	50	50	100.00
V2	stress_all	gpio_stress_all	4.125m	45.550ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	12.092us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	17.426us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.850s	918.164us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.850s	918.164us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	46.968us	20	20	100.00
		gpio_same_csr_outstanding	0.830s	121.915us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.608us	5	5	100.00
		gpio_csr_hw_reset	0.700s	15.369us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	46.968us	20	20	100.00
		gpio_same_csr_outstanding	0.830s	121.915us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.608us	5	5	100.00
		gpio_csr_hw_reset	0.700s	15.369us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	1.709ms	20	20	100.00
		gpio_sec_cm	1.440s	6.049ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	1.709ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.873m	242.370ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test gpio_stress_all_with_rand_reset has 24 failures.

    • 2.gpio_stress_all_with_rand_reset.4322727215342984706707104184477036051018156664356440254431860492417188018843
      Line 2381, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63938990037 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 63938990037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.85126119636632397225782548254070866662013968756519859559286010662546161940543
      Line 2100, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9322556944 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9322556944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

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