GPIO Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.560s	1.211ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	106.304us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.690s	93.447us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.700s	153.394us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	29.028us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	27.713us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.500s	450.904us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	29.527us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.790s	37.307us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	27.713us	20	20	100.00
		gpio_csr_aliasing	0.850s	29.527us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	63.685us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	259.853us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	30.108us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.660s	160.041us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.010s	129.752us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.910s	188.170us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.380s	1.829ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.610s	544.949us	50	50	100.00
V2	full_random	gpio_full_random	1.200s	101.618us	50	50	100.00
V2	stress_all	gpio_stress_all	4.398m	25.179ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	49.659us	50	50	100.00
V2	intr_test	gpio_intr_test	0.710s	22.656us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.030s	170.668us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.030s	170.668us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	27.713us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	116.883us	20	20	100.00
		gpio_csr_aliasing	0.850s	29.527us	5	5	100.00
		gpio_csr_hw_reset	0.660s	29.028us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	27.713us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	116.883us	20	20	100.00
		gpio_csr_aliasing	0.850s	29.527us	5	5	100.00
		gpio_csr_hw_reset	0.660s	29.028us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.520s	195.698us	20	20	100.00
		gpio_sec_cm	0.970s	364.157us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.520s	195.698us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.661m	247.398ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			944	970	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test gpio_stress_all_with_rand_reset has 26 failures.

    • 0.gpio_stress_all_with_rand_reset.74791154714076332789861034471800752903695390580956849380373150095336457642467
      Line 258, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1548702724 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1548702724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.95452494746770720812741173827973090331643626561835033622944191084797455387140
      Line 5112, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 61933892231 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 61933892231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

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