GPIO Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	350.123us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.600s	178.480us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	80.816us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.650s	223.699us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	43.464us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	29.917us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	1.530s	186.964us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	141.554us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.640s	64.040us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	29.917us	20	20	100.00
		gpio_csr_aliasing	0.880s	141.554us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.450s	67.801us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.450s	67.341us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	60.973us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.520s	50.330us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.470s	578.843us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.020s	93.278us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	30.120s	1.010ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.060s	589.757us	50	50	100.00
V2	full_random	gpio_full_random	1.210s	142.386us	50	50	100.00
V2	stress_all	gpio_stress_all	3.506m	15.779ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	14.806us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	106.867us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.070s	166.584us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.070s	166.584us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	29.917us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	109.254us	20	20	100.00
		gpio_csr_aliasing	0.880s	141.554us	5	5	100.00
		gpio_csr_hw_reset	0.700s	43.464us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	29.917us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	109.254us	20	20	100.00
		gpio_csr_aliasing	0.880s	141.554us	5	5	100.00
		gpio_csr_hw_reset	0.700s	43.464us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	115.343us	20	20	100.00
		gpio_sec_cm	1.120s	282.663us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	115.343us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	49.447m	431.838ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 1.gpio_stress_all_with_rand_reset.78904039389345158057356418994279100983241485580573563234646834257846485708282
      Line 3958, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 184144142059 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 184144142059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.gpio_stress_all_with_rand_reset.33577816243837880068688993618359830312680065988975515362018578630611719015089
      Line 2345, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44111243392 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 44111243392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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