GPIO Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	83.266us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.480s	270.624us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.640s	89.985us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	93.181us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.710s	18.432us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	34.066us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.240s	264.224us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	133.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.610s	32.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	34.066us	20	20	100.00
		gpio_csr_aliasing	0.860s	133.556us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	306.861us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	60.579us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	39.373us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.550s	108.462us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.690s	249.850us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.520s	139.546us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.670s	2.027ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.620s	1.997ms	50	50	100.00
V2	full_random	gpio_full_random	1.080s	368.068us	50	50	100.00
V2	stress_all	gpio_stress_all	4.382m	18.338ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	15.668us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	28.487us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.380s	184.681us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.380s	184.681us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	34.066us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	36.076us	20	20	100.00
		gpio_csr_aliasing	0.860s	133.556us	5	5	100.00
		gpio_csr_hw_reset	0.710s	18.432us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	34.066us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	36.076us	20	20	100.00
		gpio_csr_aliasing	0.860s	133.556us	5	5	100.00
		gpio_csr_hw_reset	0.710s	18.432us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.430s	232.849us	20	20	100.00
		gpio_sec_cm	0.970s	253.543us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.430s	232.849us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.004m	202.565ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test gpio_stress_all_with_rand_reset has 29 failures.
  - 0.gpio_stress_all_with_rand_reset.48223738480317172128573852219895815584215875797174514373841758372810239697988
    Line 2578, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21131980004 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21131980004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.7837194484752697719065320139491155599546072656431181449103913121229974088005
    Line 4744, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43795043842 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43795043842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

GPIO Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `edf2fd5092`