GPIO Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	167.530us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.540s	207.036us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	100.801us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.570s	201.434us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	38.945us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	17.053us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.580s	697.606us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	476.223us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.860s	77.047us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	17.053us	20	20	100.00
		gpio_csr_aliasing	0.860s	476.223us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	210.042us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.450s	63.834us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	197.410us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	85.494us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.740s	262.534us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.960s	95.546us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.560s	6.144ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.700s	594.377us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	172.437us	50	50	100.00
V2	stress_all	gpio_stress_all	3.865m	21.308ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	14.730us	50	50	100.00
V2	intr_test	gpio_intr_test	0.720s	45.066us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.220s	286.095us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.220s	286.095us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	17.053us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	117.409us	20	20	100.00
		gpio_csr_aliasing	0.860s	476.223us	5	5	100.00
		gpio_csr_hw_reset	0.680s	38.945us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	17.053us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	117.409us	20	20	100.00
		gpio_csr_aliasing	0.860s	476.223us	5	5	100.00
		gpio_csr_hw_reset	0.680s	38.945us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.490s	686.058us	20	20	100.00
		gpio_sec_cm	0.950s	54.764us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.490s	686.058us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.013m	487.473ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test gpio_stress_all_with_rand_reset has 29 failures.
  - 2.gpio_stress_all_with_rand_reset.46723556870543641119600617381913900634034034404646789231563951977133445210386
    Line 8355, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109983791211 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 109983791211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.103879541572659809837898694692681749693663853028359732539040370910834280348252
    Line 3788, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17457839318 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17457839318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

GPIO Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5967df933a`