GPIO Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.480s	1.040ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.450s	276.715us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.540s	162.729us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.450s	367.000us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	17.243us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	15.422us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.610s	227.537us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	123.839us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.560s	122.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	15.422us	20	20	100.00
		gpio_csr_aliasing	0.870s	123.839us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	75.639us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.450s	77.180us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	171.360us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.550s	198.168us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.540s	317.408us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.000s	92.909us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.910s	2.454ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.480s	2.148ms	50	50	100.00
V2	full_random	gpio_full_random	1.090s	93.283us	50	50	100.00
V2	stress_all	gpio_stress_all	3.727m	11.248ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	21.815us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	14.085us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.430s	1.400ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.430s	1.400ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	15.422us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	221.973us	20	20	100.00
		gpio_csr_aliasing	0.870s	123.839us	5	5	100.00
		gpio_csr_hw_reset	0.720s	17.243us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	15.422us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	221.973us	20	20	100.00
		gpio_csr_aliasing	0.870s	123.839us	5	5	100.00
		gpio_csr_hw_reset	0.720s	17.243us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	120.377us	20	20	100.00
		gpio_sec_cm	0.860s	64.536us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	120.377us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	30.143m	1.391s	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			947	970	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test gpio_stress_all_with_rand_reset has 23 failures.
  - 0.gpio_stress_all_with_rand_reset.113823935613899522705730425250418789157551703304595140603906408386970366812051
    Line 2392, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34313937510 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34313937510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.18974267964306392079296729087021214509830381706099386188935656367561831209618
    Line 5936, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 134957047971 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 134957047971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

GPIO Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d51405297e`