GPIO Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	324.446us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.560s	188.448us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.420s	156.791us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.440s	266.040us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	29.961us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	18.864us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.170s	260.042us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	37.746us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.390s	32.733us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	18.864us	20	20	100.00
		gpio_csr_aliasing	0.870s	37.746us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.550s	79.147us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.530s	170.303us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	109.742us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.640s	422.496us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.170s	243.617us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.020s	93.733us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	30.320s	843.474us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.330s	1.208ms	50	50	100.00
V2	full_random	gpio_full_random	1.150s	62.531us	50	50	100.00
V2	stress_all	gpio_stress_all	4.092m	40.514ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	14.626us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	14.564us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.090s	736.176us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.090s	736.176us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	18.864us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	157.416us	20	20	100.00
		gpio_csr_aliasing	0.870s	37.746us	5	5	100.00
		gpio_csr_hw_reset	0.680s	29.961us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	18.864us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	157.416us	20	20	100.00
		gpio_csr_aliasing	0.870s	37.746us	5	5	100.00
		gpio_csr_hw_reset	0.680s	29.961us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.470s	112.198us	20	20	100.00
		gpio_sec_cm	1.000s	102.727us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.470s	112.198us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	36.491m	186.418ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test gpio_stress_all_with_rand_reset has 31 failures.
  - 0.gpio_stress_all_with_rand_reset.54241825565139370900770869918692062300228600574256371030241796947490817497573
    Line 4885, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73990321352 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 73990321352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.13941881131046560944023910617630998458407995345550507701876975680715348831314
    Line 424, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 607239080 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 607239080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

GPIO Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`