GPIO Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	331.168us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.640s	175.155us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.570s	108.973us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.560s	78.413us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.730s	20.083us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	18.539us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.340s	278.531us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	34.790us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.740s	130.302us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	18.539us	20	20	100.00
		gpio_csr_aliasing	0.900s	34.790us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	57.606us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	146.110us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.940s	31.769us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.430s	253.743us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.560s	155.663us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.900s	96.751us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.690s	3.324ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.270s	1.719ms	50	50	100.00
V2	full_random	gpio_full_random	1.180s	252.770us	50	50	100.00
V2	stress_all	gpio_stress_all	3.414m	13.922ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	119.305us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	11.121us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.380s	198.615us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.380s	198.615us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	18.539us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	37.466us	20	20	100.00
		gpio_csr_aliasing	0.900s	34.790us	5	5	100.00
		gpio_csr_hw_reset	0.730s	20.083us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	18.539us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	37.466us	20	20	100.00
		gpio_csr_aliasing	0.900s	34.790us	5	5	100.00
		gpio_csr_hw_reset	0.730s	20.083us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	118.020us	20	20	100.00
		gpio_sec_cm	1.050s	356.247us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	118.020us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.942m	290.399ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			944	970	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test gpio_stress_all_with_rand_reset has 26 failures.
  - 2.gpio_stress_all_with_rand_reset.456912410093973541534087122697996256265893778875547687205309055597577191035
    Line 8204, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 147607016381 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 147607016381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.gpio_stress_all_with_rand_reset.19045993817678672847524333205054348768947562755806618212955528699307767094833
    Line 7495, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 160728762536 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 160728762536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.

GPIO Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a04e34f557`