GPIO Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.410s	46.429us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.580s	98.508us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.400s	288.265us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	210.208us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	16.435us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.690s	14.772us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.430s	340.727us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.770s	25.582us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.690s	35.032us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.690s	14.772us	20	20	100.00
		gpio_csr_aliasing	0.770s	25.582us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.350s	235.993us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.340s	221.596us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	56.779us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.370s	103.930us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.560s	252.906us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.600s	105.558us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.240s	1.038ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.560s	625.296us	50	50	100.00
V2	full_random	gpio_full_random	1.140s	557.318us	50	50	100.00
V2	stress_all	gpio_stress_all	3.631m	20.610ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	45.429us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	119.834us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.430s	64.500us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.430s	64.500us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.690s	14.772us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	48.484us	20	20	100.00
		gpio_csr_aliasing	0.770s	25.582us	5	5	100.00
		gpio_csr_hw_reset	0.720s	16.435us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.690s	14.772us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	48.484us	20	20	100.00
		gpio_csr_aliasing	0.770s	25.582us	5	5	100.00
		gpio_csr_hw_reset	0.720s	16.435us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.800s	419.191us	20	20	100.00
		gpio_sec_cm	0.990s	209.634us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.800s	419.191us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.546m	249.847ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test gpio_stress_all_with_rand_reset has 32 failures.
  - 1.gpio_stress_all_with_rand_reset.63794921553381868498069984572296642634234444678423597891928234334455748848135
    Line 2938, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 71021533610 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 71021533610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.49920332209499877359754770644531413187177383886681132457853458165104280110797
    Line 2539, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 545504714350 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 545504714350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.

GPIO Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`