GPIO Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.590s	230.414us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.570s	203.283us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	322.522us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.590s	97.695us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	92.029us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	105.099us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.910s	126.684us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.790s	95.232us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.440s	32.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	105.099us	20	20	100.00
		gpio_csr_aliasing	0.790s	95.232us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	145.712us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	75.964us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	49.569us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	439.522us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.650s	863.054us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.760s	359.702us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.970s	1.196ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.070s	885.242us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	147.115us	50	50	100.00
V2	stress_all	gpio_stress_all	3.697m	33.602ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	31.164us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	68.240us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.970s	367.757us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.970s	367.757us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	105.099us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	151.598us	20	20	100.00
		gpio_csr_aliasing	0.790s	95.232us	5	5	100.00
		gpio_csr_hw_reset	0.670s	92.029us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	105.099us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	151.598us	20	20	100.00
		gpio_csr_aliasing	0.790s	95.232us	5	5	100.00
		gpio_csr_hw_reset	0.670s	92.029us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	231.715us	20	20	100.00
		gpio_sec_cm	0.910s	625.141us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	231.715us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	44.995m	134.704ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test gpio_stress_all_with_rand_reset has 27 failures.
  - 1.gpio_stress_all_with_rand_reset.56671963225888826969933559788590256757681753414811741931554892495502311803100
    Line 5561, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133285008030 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 133285008030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.gpio_stress_all_with_rand_reset.13418604582769398447985174907129599952246378860157088275336609219382885724336
    Line 7907, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/5.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 228831841541 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 228831841541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

GPIO Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`