GPIO Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.560s	83.527us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.520s	84.691us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.540s	97.158us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	369.904us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	33.958us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	42.488us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.430s	1.122ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	139.147us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.760s	91.074us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	42.488us	20	20	100.00
		gpio_csr_aliasing	0.880s	139.147us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	273.927us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	55.714us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	48.204us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.620s	196.857us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	161.619us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.020s	92.356us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.700s	812.139us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.630s	563.182us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	86.727us	50	50	100.00
V2	stress_all	gpio_stress_all	3.692m	34.661ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	13.541us	50	50	100.00
V2	intr_test	gpio_intr_test	0.740s	33.214us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.290s	370.985us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.290s	370.985us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	42.488us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	41.256us	20	20	100.00
		gpio_csr_aliasing	0.880s	139.147us	5	5	100.00
		gpio_csr_hw_reset	0.650s	33.958us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	42.488us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	41.256us	20	20	100.00
		gpio_csr_aliasing	0.880s	139.147us	5	5	100.00
		gpio_csr_hw_reset	0.650s	33.958us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.520s	186.822us	20	20	100.00
		gpio_sec_cm	0.990s	173.111us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.520s	186.822us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.291m	414.427ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test gpio_stress_all_with_rand_reset has 30 failures.
  - 1.gpio_stress_all_with_rand_reset.57813253602362043228939024415917434451267334387121477733006661549091521069069
    Line 5592, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171105053848 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 171105053848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.95466541244192185068318883029175831394742121906109427409958467081853285245112
    Line 1848, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9888131787 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9888131787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.

GPIO Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `974aaab627`