GPIO Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.540s 333.967us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.460s 191.414us 50 50 100.00
gpio_smoke_en_cdc_prim 1.380s 53.993us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.500s 1.922ms 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.670s 106.121us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 14.925us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 2.950s 293.103us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.800s 33.729us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.560s 66.413us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 14.925us 20 20 100.00
gpio_csr_aliasing 0.800s 33.729us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.390s 70.020us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.290s 80.814us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.980s 58.114us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.460s 334.626us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.510s 125.055us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.650s 103.830us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.980s 1.737ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.880s 517.603us 50 50 100.00
V2 full_random gpio_full_random 1.100s 196.827us 50 50 100.00
V2 stress_all gpio_stress_all 3.327m 86.615ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 37.736us 50 50 100.00
V2 intr_test gpio_intr_test 0.660s 34.232us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.140s 210.142us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.140s 210.142us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 14.925us 20 20 100.00
gpio_same_csr_outstanding 0.910s 110.639us 20 20 100.00
gpio_csr_aliasing 0.800s 33.729us 5 5 100.00
gpio_csr_hw_reset 0.670s 106.121us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 14.925us 20 20 100.00
gpio_same_csr_outstanding 0.910s 110.639us 20 20 100.00
gpio_csr_aliasing 0.800s 33.729us 5 5 100.00
gpio_csr_hw_reset 0.670s 106.121us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.440s 518.278us 20 20 100.00
gpio_sec_cm 0.960s 610.893us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.440s 518.278us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 51.031m 777.133ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 940 970 96.91

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results