GPIO Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.730s 1.552ms 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.550s 82.574us 50 50 100.00
gpio_smoke_en_cdc_prim 1.460s 336.615us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.450s 96.492us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.660s 202.990us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.630s 74.829us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.160s 3.060ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.820s 143.080us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.860s 41.731us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.630s 74.829us 20 20 100.00
gpio_csr_aliasing 0.820s 143.080us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.350s 269.895us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.460s 59.414us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.040s 197.174us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.500s 286.306us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.900s 442.414us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.620s 382.575us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.070s 5.215ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.190s 136.919us 50 50 100.00
V2 full_random gpio_full_random 1.040s 77.227us 50 50 100.00
V2 stress_all gpio_stress_all 3.840m 69.988ms 50 50 100.00
V2 alert_test gpio_alert_test 0.690s 38.092us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 14.850us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.080s 262.407us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.080s 262.407us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.630s 74.829us 20 20 100.00
gpio_same_csr_outstanding 0.950s 43.896us 20 20 100.00
gpio_csr_aliasing 0.820s 143.080us 5 5 100.00
gpio_csr_hw_reset 0.660s 202.990us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.630s 74.829us 20 20 100.00
gpio_same_csr_outstanding 0.950s 43.896us 20 20 100.00
gpio_csr_aliasing 0.820s 143.080us 5 5 100.00
gpio_csr_hw_reset 0.660s 202.990us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.500s 1.211ms 20 20 100.00
gpio_sec_cm 0.900s 304.168us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.500s 1.211ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 45.677m 248.825ms 13 50 26.00
V3 TOTAL 13 50 26.00
TOTAL 933 970 96.19

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results