GPIO Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.530s 91.023us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.700s 94.352us 50 50 100.00
gpio_smoke_en_cdc_prim 1.530s 110.517us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.660s 393.368us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 126.028us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.650s 26.037us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.390s 523.203us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.850s 113.463us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.680s 34.531us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.650s 26.037us 20 20 100.00
gpio_csr_aliasing 0.850s 113.463us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.400s 229.637us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.550s 256.258us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.010s 54.266us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.520s 103.494us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 4.220s 1.668ms 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 4.170s 178.838us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 29.080s 2.150ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.720s 1.751ms 50 50 100.00
V2 full_random gpio_full_random 1.090s 310.862us 50 50 100.00
V2 stress_all gpio_stress_all 4.003m 62.111ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 12.302us 50 50 100.00
V2 intr_test gpio_intr_test 0.660s 13.066us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.040s 615.301us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.040s 615.301us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.650s 26.037us 20 20 100.00
gpio_same_csr_outstanding 0.880s 70.063us 20 20 100.00
gpio_csr_aliasing 0.850s 113.463us 5 5 100.00
gpio_csr_hw_reset 0.690s 126.028us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.650s 26.037us 20 20 100.00
gpio_same_csr_outstanding 0.880s 70.063us 20 20 100.00
gpio_csr_aliasing 0.850s 113.463us 5 5 100.00
gpio_csr_hw_reset 0.690s 126.028us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.470s 122.946us 20 20 100.00
gpio_sec_cm 1.010s 89.948us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.470s 122.946us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 33.803m 88.067ms 24 50 48.00
V3 TOTAL 24 50 48.00
TOTAL 944 970 97.32

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results