GPIO Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	142.752us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.520s	82.024us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.510s	85.499us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.650s	425.522us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	31.291us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	14.657us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.530s	1.311ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	115.588us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.610s	288.938us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	14.657us	20	20	100.00
		gpio_csr_aliasing	0.870s	115.588us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	254.986us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.430s	70.106us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.930s	91.130us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.400s	99.768us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.720s	224.093us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.620s	170.203us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.150s	1.000ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.620s	564.337us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	357.080us	50	50	100.00
V2	stress_all	gpio_stress_all	3.676m	16.570ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	15.754us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	42.482us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.870s	530.508us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.870s	530.508us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	14.657us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	171.953us	20	20	100.00
		gpio_csr_aliasing	0.870s	115.588us	5	5	100.00
		gpio_csr_hw_reset	0.690s	31.291us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	14.657us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	171.953us	20	20	100.00
		gpio_csr_aliasing	0.870s	115.588us	5	5	100.00
		gpio_csr_hw_reset	0.690s	31.291us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.490s	133.087us	20	20	100.00
		gpio_sec_cm	0.950s	95.977us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.490s	133.087us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.333m	235.270ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test gpio_stress_all_with_rand_reset has 27 failures.
  - 0.gpio_stress_all_with_rand_reset.85992406527287801607181984000924924251298760499614809445163356386986561776091
    Line 3375, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25560341388 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25560341388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.43714269124226022755176071492523683846773837138865376399657118839256990641931
    Line 7285, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69659170223 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 69659170223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

GPIO Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0bfa990ddc`