GPIO Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.450s 165.867us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.470s 379.602us 50 50 100.00
gpio_smoke_en_cdc_prim 1.540s 100.154us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.540s 83.433us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.670s 18.264us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.670s 45.061us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.290s 1.026ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.850s 213.229us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.590s 159.961us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.670s 45.061us 20 20 100.00
gpio_csr_aliasing 0.850s 213.229us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.320s 77.666us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.300s 67.402us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.010s 48.860us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.490s 99.494us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.620s 311.652us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.930s 165.938us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.130s 1.654ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.260s 397.886us 50 50 100.00
V2 full_random gpio_full_random 1.130s 385.217us 50 50 100.00
V2 stress_all gpio_stress_all 3.948m 55.682ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 23.765us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 50.166us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.650s 154.037us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.650s 154.037us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.670s 45.061us 20 20 100.00
gpio_same_csr_outstanding 0.900s 40.202us 20 20 100.00
gpio_csr_aliasing 0.850s 213.229us 5 5 100.00
gpio_csr_hw_reset 0.670s 18.264us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.670s 45.061us 20 20 100.00
gpio_same_csr_outstanding 0.900s 40.202us 20 20 100.00
gpio_csr_aliasing 0.850s 213.229us 5 5 100.00
gpio_csr_hw_reset 0.670s 18.264us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.470s 120.256us 20 20 100.00
gpio_sec_cm 0.970s 79.981us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.470s 120.256us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 47.997m 208.465ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 949 970 97.84

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results