GPIO Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.380s	88.700us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	84.413us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.450s	50.490us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.540s	55.777us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.630s	16.005us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	61.388us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.420s	629.294us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.960s	38.588us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.840s	40.552us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	61.388us	20	20	100.00
		gpio_csr_aliasing	0.960s	38.588us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	79.554us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	130.936us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	198.790us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.450s	324.993us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.220s	112.306us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.600s	104.406us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.170s	559.829us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.020s	3.053ms	50	50	100.00
V2	full_random	gpio_full_random	1.080s	169.449us	50	50	100.00
V2	stress_all	gpio_stress_all	3.612m	65.778ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.600s	41.729us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	44.226us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.070s	250.110us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.070s	250.110us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	61.388us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	35.490us	20	20	100.00
		gpio_csr_aliasing	0.960s	38.588us	5	5	100.00
		gpio_csr_hw_reset	0.630s	16.005us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	61.388us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	35.490us	20	20	100.00
		gpio_csr_aliasing	0.960s	38.588us	5	5	100.00
		gpio_csr_hw_reset	0.630s	16.005us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	131.053us	20	20	100.00
		gpio_sec_cm	1.590s	2.520ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	131.053us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	39.618m	123.724ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test gpio_stress_all_with_rand_reset has 27 failures.
  - 1.gpio_stress_all_with_rand_reset.60061563120721800177486728144515537377117539873922358711324324487916658702686
    Line 6587, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49211890140 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49211890140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.8640250685022959710709899326900552931554897206205179643584776781787334754439
    Line 2810, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9753207525 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9753207525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

GPIO Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a47820eb4c`