GPIO Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.540s 219.912us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.400s 144.255us 50 50 100.00
gpio_smoke_en_cdc_prim 1.750s 100.235us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.480s 54.166us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 15.915us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.670s 12.883us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.470s 326.116us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.850s 288.894us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.800s 39.511us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.670s 12.883us 20 20 100.00
gpio_csr_aliasing 0.850s 288.894us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.400s 69.806us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.420s 76.999us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.030s 100.919us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.600s 172.590us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.740s 126.814us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.760s 100.148us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.590s 865.534us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.570s 3.485ms 50 50 100.00
V2 full_random gpio_full_random 1.070s 96.725us 50 50 100.00
V2 stress_all gpio_stress_all 3.354m 77.003ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 15.508us 50 50 100.00
V2 intr_test gpio_intr_test 0.640s 23.882us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.800s 112.851us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.800s 112.851us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.670s 12.883us 20 20 100.00
gpio_same_csr_outstanding 0.850s 69.550us 20 20 100.00
gpio_csr_aliasing 0.850s 288.894us 5 5 100.00
gpio_csr_hw_reset 0.690s 15.915us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.670s 12.883us 20 20 100.00
gpio_same_csr_outstanding 0.850s 69.550us 20 20 100.00
gpio_csr_aliasing 0.850s 288.894us 5 5 100.00
gpio_csr_hw_reset 0.690s 15.915us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.530s 117.911us 20 20 100.00
gpio_sec_cm 1.010s 277.757us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.530s 117.911us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 55.673m 722.379ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 948 970 97.73

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results