GPIO Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.630s	744.828us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	91.444us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.520s	152.898us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	91.735us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	17.594us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	27.896us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.510s	380.105us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.950s	32.415us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.600s	36.856us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	27.896us	20	20	100.00
		gpio_csr_aliasing	0.950s	32.415us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	74.882us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	222.828us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.070s	90.488us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.610s	107.553us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.770s	258.541us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.810s	88.352us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.600s	1.009ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.370s	798.859us	50	50	100.00
V2	full_random	gpio_full_random	1.170s	107.815us	50	50	100.00
V2	stress_all	gpio_stress_all	3.736m	15.564ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	43.912us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	13.123us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.220s	66.293us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.220s	66.293us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	27.896us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	72.752us	20	20	100.00
		gpio_csr_aliasing	0.950s	32.415us	5	5	100.00
		gpio_csr_hw_reset	0.670s	17.594us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	27.896us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	72.752us	20	20	100.00
		gpio_csr_aliasing	0.950s	32.415us	5	5	100.00
		gpio_csr_hw_reset	0.670s	17.594us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	227.542us	20	20	100.00
		gpio_sec_cm	0.870s	75.797us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	227.542us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.824m	227.310ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test gpio_stress_all_with_rand_reset has 30 failures.
  - 0.gpio_stress_all_with_rand_reset.15640418963531736132067395724289686095466602881277205322990812982404018362875
    Line 4016, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26680091729 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26680091729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.43580942290302722034175337592269457897893309403088662397169580055932057565508
    Line 3418, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35694595399 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35694595399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.

GPIO Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`