GPIO Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.660s 75.057us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.470s 94.744us 50 50 100.00
gpio_smoke_en_cdc_prim 1.450s 464.669us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.420s 763.475us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.670s 32.134us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.680s 17.031us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.050s 1.144ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.730s 47.844us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 2.140s 326.027us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.680s 17.031us 20 20 100.00
gpio_csr_aliasing 0.730s 47.844us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.300s 37.529us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.360s 64.059us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.980s 126.835us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.420s 192.846us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.690s 239.201us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.650s 179.335us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.050s 784.291us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.320s 2.051ms 50 50 100.00
V2 full_random gpio_full_random 1.140s 93.454us 50 50 100.00
V2 stress_all gpio_stress_all 3.837m 16.139ms 50 50 100.00
V2 alert_test gpio_alert_test 0.620s 40.310us 50 50 100.00
V2 intr_test gpio_intr_test 0.680s 17.509us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.040s 156.472us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.040s 156.472us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.680s 17.031us 20 20 100.00
gpio_same_csr_outstanding 0.880s 143.151us 20 20 100.00
gpio_csr_aliasing 0.730s 47.844us 5 5 100.00
gpio_csr_hw_reset 0.670s 32.134us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.680s 17.031us 20 20 100.00
gpio_same_csr_outstanding 0.880s 143.151us 20 20 100.00
gpio_csr_aliasing 0.730s 47.844us 5 5 100.00
gpio_csr_hw_reset 0.670s 32.134us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.470s 228.162us 20 20 100.00
gpio_sec_cm 0.900s 55.863us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.470s 228.162us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 43.977m 107.260ms 23 50 46.00
V3 TOTAL 23 50 46.00
TOTAL 943 970 97.22

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results