39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | gpio_smoke | 1.460s | 104.103us | 50 | 50 | 100.00 |
| gpio_smoke_no_pullup_pulldown | 1.540s | 355.207us | 50 | 50 | 100.00 | ||
| gpio_smoke_en_cdc_prim | 1.450s | 496.612us | 50 | 50 | 100.00 | ||
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.540s | 375.155us | 50 | 50 | 100.00 | ||
| V1 | csr_hw_reset | gpio_csr_hw_reset | 0.690s | 24.159us | 5 | 5 | 100.00 |
| V1 | csr_rw | gpio_csr_rw | 0.670s | 17.170us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | gpio_csr_bit_bash | 3.350s | 2.444ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | gpio_csr_aliasing | 0.830s | 30.920us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.690s | 150.768us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.670s | 17.170us | 20 | 20 | 100.00 |
| gpio_csr_aliasing | 0.830s | 30.920us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | direct_and_masked_out | gpio_random_dout_din | 1.430s | 76.908us | 50 | 50 | 100.00 |
| gpio_random_dout_din_no_pullup_pulldown | 1.420s | 147.664us | 50 | 50 | 100.00 | ||
| V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.940s | 174.843us | 50 | 50 | 100.00 |
| V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.370s | 101.017us | 50 | 50 | 100.00 |
| V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.550s | 411.542us | 50 | 50 | 100.00 |
| V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.790s | 178.604us | 50 | 50 | 100.00 |
| V2 | noise_filter_stress | gpio_filter_stress | 27.070s | 928.788us | 50 | 50 | 100.00 |
| V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 6.280s | 2.964ms | 50 | 50 | 100.00 |
| V2 | full_random | gpio_full_random | 1.100s | 191.491us | 50 | 50 | 100.00 |
| V2 | stress_all | gpio_stress_all | 3.975m | 68.787ms | 50 | 50 | 100.00 |
| V2 | alert_test | gpio_alert_test | 0.680s | 14.883us | 50 | 50 | 100.00 |
| V2 | intr_test | gpio_intr_test | 0.670s | 11.531us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | gpio_tl_errors | 2.890s | 544.653us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | gpio_tl_errors | 2.890s | 544.653us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | gpio_csr_rw | 0.670s | 17.170us | 20 | 20 | 100.00 |
| gpio_same_csr_outstanding | 0.880s | 76.669us | 20 | 20 | 100.00 | ||
| gpio_csr_aliasing | 0.830s | 30.920us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.690s | 24.159us | 5 | 5 | 100.00 | ||
| V2 | tl_d_partial_access | gpio_csr_rw | 0.670s | 17.170us | 20 | 20 | 100.00 |
| gpio_same_csr_outstanding | 0.880s | 76.669us | 20 | 20 | 100.00 | ||
| gpio_csr_aliasing | 0.830s | 30.920us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.690s | 24.159us | 5 | 5 | 100.00 | ||
| V2 | TOTAL | 640 | 640 | 100.00 | |||
| V2S | tl_intg_err | gpio_tl_intg_err | 1.480s | 229.412us | 20 | 20 | 100.00 |
| gpio_sec_cm | 1.020s | 291.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.480s | 229.412us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 39.891m | 409.263ms | 26 | 50 | 52.00 |
| V3 | TOTAL | 26 | 50 | 52.00 | |||
| TOTAL | 946 | 970 | 97.53 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 14 | 14 | 14 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.63 | 99.06 | 99.24 | 100.00 | -- | 99.80 | 99.68 | 99.99 |
UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
1.gpio_stress_all_with_rand_reset.101860025634003380933463969744435047513638796529105335457888221025654827083225
Line 5111, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36382591789 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36382591789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.gpio_stress_all_with_rand_reset.98763082674559775010267444529923120275904604146527795473087071063691785527440
Line 4907, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40784495561 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 40784495561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
8.gpio_stress_all_with_rand_reset.16614116816364821033530044899011203078343471171276434188764863634009426186430
Line 7443, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 470833027073 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 470833027073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---