GPIO Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.540s 217.348us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.540s 343.341us 50 50 100.00
gpio_smoke_en_cdc_prim 1.610s 51.062us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.530s 205.429us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.650s 26.521us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 60.855us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 2.360s 2.137ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.760s 28.004us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.610s 108.039us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 60.855us 20 20 100.00
gpio_csr_aliasing 0.760s 28.004us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.440s 77.819us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.290s 220.434us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.010s 63.061us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.550s 198.854us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.650s 643.822us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.850s 181.228us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 29.480s 2.070ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.340s 367.721us 50 50 100.00
V2 full_random gpio_full_random 1.160s 89.867us 50 50 100.00
V2 stress_all gpio_stress_all 3.726m 74.824ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 18.378us 50 50 100.00
V2 intr_test gpio_intr_test 0.700s 19.396us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.270s 65.152us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.270s 65.152us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 60.855us 20 20 100.00
gpio_same_csr_outstanding 0.870s 133.860us 20 20 100.00
gpio_csr_aliasing 0.760s 28.004us 5 5 100.00
gpio_csr_hw_reset 0.650s 26.521us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 60.855us 20 20 100.00
gpio_same_csr_outstanding 0.870s 133.860us 20 20 100.00
gpio_csr_aliasing 0.760s 28.004us 5 5 100.00
gpio_csr_hw_reset 0.650s 26.521us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.530s 708.529us 20 20 100.00
gpio_sec_cm 1.150s 1.124ms 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.530s 708.529us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 43.702m 336.725ms 21 50 42.00
V3 TOTAL 21 50 42.00
TOTAL 941 970 97.01

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results