GPIO Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.450s	120.275us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.560s	193.018us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.510s	271.347us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.430s	153.229us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.630s	28.892us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.630s	43.729us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.260s	262.321us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	35.504us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.550s	177.726us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.630s	43.729us	20	20	100.00
		gpio_csr_aliasing	0.920s	35.504us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	219.356us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.340s	222.141us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	164.336us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.470s	160.368us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.360s	149.957us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.680s	118.764us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.620s	2.413ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.260s	781.689us	50	50	100.00
V2	full_random	gpio_full_random	1.110s	78.394us	50	50	100.00
V2	stress_all	gpio_stress_all	4.012m	326.163ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	43.725us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	14.908us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.160s	194.427us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.160s	194.427us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.630s	43.729us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	222.369us	20	20	100.00
		gpio_csr_aliasing	0.920s	35.504us	5	5	100.00
		gpio_csr_hw_reset	0.630s	28.892us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.630s	43.729us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	222.369us	20	20	100.00
		gpio_csr_aliasing	0.920s	35.504us	5	5	100.00
		gpio_csr_hw_reset	0.630s	28.892us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.440s	455.602us	20	20	100.00
		gpio_sec_cm	0.970s	107.796us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.440s	455.602us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.547m	1.015s	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test gpio_stress_all_with_rand_reset has 28 failures.
  - 3.gpio_stress_all_with_rand_reset.75228099052781443642814991308372108550256022050859211180385383975311504240426
    Line 3575, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63442724794 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 63442724794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.gpio_stress_all_with_rand_reset.87751701918211959211572728501356364967365003455939778452482583030424854256807
    Line 10145, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48832082564 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48832082564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.

GPIO Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9b7e615a7`