GPIO Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.670s	1.066ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	83.054us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.610s	312.314us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.520s	203.478us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	15.579us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	11.881us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.510s	1.775ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	41.798us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.710s	72.835us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	11.881us	20	20	100.00
		gpio_csr_aliasing	0.900s	41.798us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.450s	75.875us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	160.231us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.980s	53.432us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	357.901us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.700s	254.376us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.700s	89.268us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.860s	6.600ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.270s	1.085ms	50	50	100.00
V2	full_random	gpio_full_random	1.180s	103.272us	50	50	100.00
V2	stress_all	gpio_stress_all	3.633m	38.822ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	21.620us	50	50	100.00
V2	intr_test	gpio_intr_test	0.730s	16.285us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.580s	356.078us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.580s	356.078us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	11.881us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	63.279us	20	20	100.00
		gpio_csr_aliasing	0.900s	41.798us	5	5	100.00
		gpio_csr_hw_reset	0.680s	15.579us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	11.881us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	63.279us	20	20	100.00
		gpio_csr_aliasing	0.900s	41.798us	5	5	100.00
		gpio_csr_hw_reset	0.680s	15.579us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.460s	793.776us	20	20	100.00
		gpio_sec_cm	0.950s	297.588us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.460s	793.776us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.178m	379.309ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			936	970	96.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test gpio_stress_all_with_rand_reset has 34 failures.
  - 0.gpio_stress_all_with_rand_reset.34679200574371505553343173561802820320450760592690515313255360333621423789478
    Line 8108, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127170237236 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 127170237236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.77914377821497464348196666285127068650420945826920813516857476243273954834943
    Line 504, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3232955367 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3232955367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.

GPIO Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `625f353e9c`