GPIO Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.400s 69.288us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.550s 205.553us 50 50 100.00
gpio_smoke_en_cdc_prim 1.450s 61.556us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.440s 95.608us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.650s 52.395us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.660s 25.310us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 2.450s 574.720us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.880s 67.395us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.800s 39.169us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.660s 25.310us 20 20 100.00
gpio_csr_aliasing 0.880s 67.395us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.300s 454.298us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.420s 68.689us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.940s 103.309us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.490s 208.881us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.470s 578.652us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.680s 365.746us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.950s 866.158us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.180s 8.548ms 50 50 100.00
V2 full_random gpio_full_random 1.170s 61.775us 50 50 100.00
V2 stress_all gpio_stress_all 3.635m 17.456ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 56.660us 50 50 100.00
V2 intr_test gpio_intr_test 0.640s 48.567us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.830s 137.621us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.830s 137.621us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.660s 25.310us 20 20 100.00
gpio_same_csr_outstanding 0.850s 77.210us 20 20 100.00
gpio_csr_aliasing 0.880s 67.395us 5 5 100.00
gpio_csr_hw_reset 0.650s 52.395us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.660s 25.310us 20 20 100.00
gpio_same_csr_outstanding 0.850s 77.210us 20 20 100.00
gpio_csr_aliasing 0.880s 67.395us 5 5 100.00
gpio_csr_hw_reset 0.650s 52.395us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.430s 214.112us 20 20 100.00
gpio_sec_cm 0.920s 328.604us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.430s 214.112us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 44.478m 141.464ms 24 50 48.00
V3 TOTAL 24 50 48.00
TOTAL 944 970 97.32

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results