GPIO Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.460s 70.686us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.630s 179.921us 50 50 100.00
gpio_smoke_en_cdc_prim 1.530s 313.412us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.550s 325.007us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.710s 13.565us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.710s 15.375us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.440s 1.609ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.850s 18.685us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.070s 78.312us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.710s 15.375us 20 20 100.00
gpio_csr_aliasing 0.850s 18.685us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.420s 65.151us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.480s 35.257us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.980s 58.363us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.510s 422.315us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.580s 117.473us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 4.180s 192.157us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.370s 1.263ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 7.010s 1.312ms 50 50 100.00
V2 full_random gpio_full_random 1.140s 84.068us 50 50 100.00
V2 stress_all gpio_stress_all 3.522m 21.707ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 24.120us 50 50 100.00
V2 intr_test gpio_intr_test 0.810s 49.056us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.340s 1.147ms 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.340s 1.147ms 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.710s 15.375us 20 20 100.00
gpio_same_csr_outstanding 0.980s 42.479us 20 20 100.00
gpio_csr_aliasing 0.850s 18.685us 5 5 100.00
gpio_csr_hw_reset 0.710s 13.565us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.710s 15.375us 20 20 100.00
gpio_same_csr_outstanding 0.980s 42.479us 20 20 100.00
gpio_csr_aliasing 0.850s 18.685us 5 5 100.00
gpio_csr_hw_reset 0.710s 13.565us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.500s 124.875us 20 20 100.00
gpio_sec_cm 1.020s 87.671us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.500s 124.875us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 44.291m 296.936ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 948 970 97.73

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results