GPIO Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.570s 470.399us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.420s 76.616us 50 50 100.00
gpio_smoke_en_cdc_prim 1.580s 173.636us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.360s 88.541us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 73.753us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.720s 16.306us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.130s 1.309ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.780s 83.280us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.840s 41.243us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.720s 16.306us 20 20 100.00
gpio_csr_aliasing 0.780s 83.280us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.350s 65.086us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.230s 62.597us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.000s 179.276us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.450s 361.339us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.380s 124.361us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.610s 1.094ms 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.340s 933.160us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.190s 459.251us 50 50 100.00
V2 full_random gpio_full_random 1.080s 185.389us 50 50 100.00
V2 stress_all gpio_stress_all 3.879m 34.301ms 50 50 100.00
V2 alert_test gpio_alert_test 0.610s 16.809us 50 50 100.00
V2 intr_test gpio_intr_test 0.710s 15.593us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.940s 210.103us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.940s 210.103us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.720s 16.306us 20 20 100.00
gpio_same_csr_outstanding 0.890s 44.425us 20 20 100.00
gpio_csr_aliasing 0.780s 83.280us 5 5 100.00
gpio_csr_hw_reset 0.690s 73.753us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.720s 16.306us 20 20 100.00
gpio_same_csr_outstanding 0.890s 44.425us 20 20 100.00
gpio_csr_aliasing 0.780s 83.280us 5 5 100.00
gpio_csr_hw_reset 0.690s 73.753us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.960s 1.067ms 20 20 100.00
gpio_sec_cm 1.020s 553.721us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.960s 1.067ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 40.067m 98.551ms 15 50 30.00
V3 TOTAL 15 50 30.00
TOTAL 935 970 96.39

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results