GPIO Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	354.638us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.610s	251.311us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.570s	92.312us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.750s	373.800us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	20.878us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	12.698us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.520s	946.844us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.810s	62.772us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.850s	38.062us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	12.698us	20	20	100.00
		gpio_csr_aliasing	0.810s	62.772us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	227.025us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	64.056us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	270.512us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.450s	180.209us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.520s	177.642us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.810s	91.672us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.650s	3.876ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.750s	698.432us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	372.715us	50	50	100.00
V2	stress_all	gpio_stress_all	3.474m	13.947ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	15.031us	50	50	100.00
V2	intr_test	gpio_intr_test	0.720s	57.505us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.130s	54.414us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.130s	54.414us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	12.698us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	71.277us	20	20	100.00
		gpio_csr_aliasing	0.810s	62.772us	5	5	100.00
		gpio_csr_hw_reset	0.700s	20.878us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	12.698us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	71.277us	20	20	100.00
		gpio_csr_aliasing	0.810s	62.772us	5	5	100.00
		gpio_csr_hw_reset	0.700s	20.878us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.590s	127.865us	20	20	100.00
		gpio_sec_cm	0.960s	457.979us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.590s	127.865us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.139m	348.336ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			949	970	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test gpio_stress_all_with_rand_reset has 21 failures.
  - 2.gpio_stress_all_with_rand_reset.34428271524047158598225109567217876837358121119103945515305060395174403001268
    Line 4767, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50544820067 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50544820067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.76941704029877730076750307904909913975055910896850219752022302962071072248794
    Line 9656, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42504377248 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42504377248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

GPIO Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e4c5daa580`