GPIO Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.600s	130.874us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.540s	107.340us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.540s	381.199us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.470s	182.252us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	22.300us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	14.797us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.240s	519.356us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	19.401us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.770s	196.429us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	14.797us	20	20	100.00
		gpio_csr_aliasing	0.840s	19.401us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.420s	34.305us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.300s	122.901us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.030s	188.112us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	173.016us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.350s	112.750us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.730s	96.332us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.340s	883.721us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.100s	458.445us	50	50	100.00
V2	full_random	gpio_full_random	1.080s	75.383us	50	50	100.00
V2	stress_all	gpio_stress_all	4.255m	99.384ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	16.421us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	55.083us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.820s	137.236us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.820s	137.236us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	14.797us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	63.477us	20	20	100.00
		gpio_csr_aliasing	0.840s	19.401us	5	5	100.00
		gpio_csr_hw_reset	0.720s	22.300us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	14.797us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	63.477us	20	20	100.00
		gpio_csr_aliasing	0.840s	19.401us	5	5	100.00
		gpio_csr_hw_reset	0.720s	22.300us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	113.277us	20	20	100.00
		gpio_sec_cm	0.990s	202.924us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	113.277us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.951m	116.677ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			947	970	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test gpio_stress_all_with_rand_reset has 23 failures.
  - 0.gpio_stress_all_with_rand_reset.5193665671394199057599226392002601786202769180129437573559713884315944087095
    Line 2462, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16195942184 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16195942184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.29411258950512435041449920219236467692246921818021913691540033327174509776747
    Line 4628, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18664013161 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18664013161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

GPIO Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5fd4ecc0fc`