GPIO Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.410s 101.108us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.430s 421.344us 50 50 100.00
gpio_smoke_en_cdc_prim 1.420s 174.077us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.590s 210.444us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.670s 62.334us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.660s 17.100us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.150s 318.259us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.760s 26.207us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.250s 80.265us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.660s 17.100us 20 20 100.00
gpio_csr_aliasing 0.760s 26.207us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.300s 189.065us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.430s 81.399us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.020s 55.625us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.470s 107.410us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.520s 121.317us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.670s 265.312us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.350s 4.425ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.220s 515.961us 50 50 100.00
V2 full_random gpio_full_random 1.120s 575.290us 50 50 100.00
V2 stress_all gpio_stress_all 4.019m 22.204ms 50 50 100.00
V2 alert_test gpio_alert_test 0.620s 19.117us 50 50 100.00
V2 intr_test gpio_intr_test 0.660s 80.046us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.750s 122.736us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.750s 122.736us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.660s 17.100us 20 20 100.00
gpio_same_csr_outstanding 0.870s 38.927us 20 20 100.00
gpio_csr_aliasing 0.760s 26.207us 5 5 100.00
gpio_csr_hw_reset 0.670s 62.334us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.660s 17.100us 20 20 100.00
gpio_same_csr_outstanding 0.870s 38.927us 20 20 100.00
gpio_csr_aliasing 0.760s 26.207us 5 5 100.00
gpio_csr_hw_reset 0.670s 62.334us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.500s 419.861us 20 20 100.00
gpio_sec_cm 0.990s 470.832us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.500s 419.861us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 39.667m 473.511ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 949 970 97.84

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results