GPIO Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	85.672us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	353.587us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.610s	362.236us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.550s	198.301us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	22.664us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	15.387us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.080s	503.972us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	101.224us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.490s	60.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	15.387us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.224us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.330s	125.228us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	112.744us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	288.202us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.500s	572.888us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.700s	118.527us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.740s	365.766us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.480s	518.776us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.530s	406.700us	50	50	100.00
V2	full_random	gpio_full_random	1.180s	100.712us	50	50	100.00
V2	stress_all	gpio_stress_all	4.254m	427.677ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	25.336us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	15.312us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.180s	147.340us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.180s	147.340us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	15.387us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	50.084us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.224us	5	5	100.00
		gpio_csr_hw_reset	0.690s	22.664us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	15.387us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	50.084us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.224us	5	5	100.00
		gpio_csr_hw_reset	0.690s	22.664us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.700s	1.272ms	20	20	100.00
		gpio_sec_cm	1.020s	373.796us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.700s	1.272ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	45.523m	496.638ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test gpio_stress_all_with_rand_reset has 31 failures.
  - 0.gpio_stress_all_with_rand_reset.103582456279251196992022757884027324118197280346336937324740457821211746153712
    Line 5333, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26888476741 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26888476741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.52611325032604501322891735479686639229794510945673046860608434005102879251169
    Line 5409, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 224925958895 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 224925958895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

GPIO Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3707c48f56`