GPIO Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.470s 248.077us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.500s 313.482us 50 50 100.00
gpio_smoke_en_cdc_prim 1.650s 101.644us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.540s 155.919us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.700s 60.213us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 14.375us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 2.690s 220.566us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.890s 35.420us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.500s 30.949us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 14.375us 20 20 100.00
gpio_csr_aliasing 0.890s 35.420us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.430s 59.160us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.450s 241.032us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.990s 44.534us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.460s 112.978us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.750s 258.171us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.860s 159.523us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 30.990s 1.051ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.750s 3.858ms 50 50 100.00
V2 full_random gpio_full_random 1.180s 988.768us 50 50 100.00
V2 stress_all gpio_stress_all 4.570m 41.340ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 17.047us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 14.789us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.170s 819.888us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.170s 819.888us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 14.375us 20 20 100.00
gpio_same_csr_outstanding 0.940s 35.415us 20 20 100.00
gpio_csr_aliasing 0.890s 35.420us 5 5 100.00
gpio_csr_hw_reset 0.700s 60.213us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 14.375us 20 20 100.00
gpio_same_csr_outstanding 0.940s 35.415us 20 20 100.00
gpio_csr_aliasing 0.890s 35.420us 5 5 100.00
gpio_csr_hw_reset 0.700s 60.213us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.470s 420.808us 20 20 100.00
gpio_sec_cm 1.430s 883.305us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.470s 420.808us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 46.311m 131.119ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 947 970 97.63

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results