GPIO Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.500s 216.539us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.580s 94.268us 50 50 100.00
gpio_smoke_en_cdc_prim 1.500s 230.272us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.690s 427.822us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.680s 24.468us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.700s 15.178us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.610s 5.286ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.770s 44.839us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.610s 102.648us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.700s 15.178us 20 20 100.00
gpio_csr_aliasing 0.770s 44.839us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.410s 201.848us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.440s 73.190us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.070s 152.403us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.510s 432.132us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.940s 260.237us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.900s 189.444us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.440s 779.232us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.740s 5.693ms 50 50 100.00
V2 full_random gpio_full_random 1.220s 99.355us 50 50 100.00
V2 stress_all gpio_stress_all 3.806m 15.481ms 50 50 100.00
V2 alert_test gpio_alert_test 0.670s 14.624us 50 50 100.00
V2 intr_test gpio_intr_test 0.690s 38.841us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.350s 921.865us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.350s 921.865us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.700s 15.178us 20 20 100.00
gpio_same_csr_outstanding 0.880s 39.167us 20 20 100.00
gpio_csr_aliasing 0.770s 44.839us 5 5 100.00
gpio_csr_hw_reset 0.680s 24.468us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.700s 15.178us 20 20 100.00
gpio_same_csr_outstanding 0.880s 39.167us 20 20 100.00
gpio_csr_aliasing 0.770s 44.839us 5 5 100.00
gpio_csr_hw_reset 0.680s 24.468us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.620s 239.308us 20 20 100.00
gpio_sec_cm 0.970s 338.069us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.620s 239.308us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 40.894m 947.272ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 940 970 96.91

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results