GPIO Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.500s 151.024us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.460s 386.499us 50 50 100.00
gpio_smoke_en_cdc_prim 1.420s 375.848us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.500s 78.424us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.650s 35.764us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.670s 13.599us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.430s 337.536us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.870s 232.592us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.360s 30.346us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.670s 13.599us 20 20 100.00
gpio_csr_aliasing 0.870s 232.592us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.380s 143.220us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.270s 517.354us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.940s 79.500us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.440s 1.838ms 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.790s 458.864us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.900s 385.056us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.420s 1.587ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.890s 1.005ms 50 50 100.00
V2 full_random gpio_full_random 1.130s 455.478us 50 50 100.00
V2 stress_all gpio_stress_all 3.877m 63.655ms 50 50 100.00
V2 alert_test gpio_alert_test 0.630s 12.873us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 16.961us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.210s 118.298us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.210s 118.298us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.670s 13.599us 20 20 100.00
gpio_same_csr_outstanding 0.880s 65.384us 20 20 100.00
gpio_csr_aliasing 0.870s 232.592us 5 5 100.00
gpio_csr_hw_reset 0.650s 35.764us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.670s 13.599us 20 20 100.00
gpio_same_csr_outstanding 0.880s 65.384us 20 20 100.00
gpio_csr_aliasing 0.870s 232.592us 5 5 100.00
gpio_csr_hw_reset 0.650s 35.764us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.430s 353.671us 20 20 100.00
gpio_sec_cm 0.970s 184.491us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.430s 353.671us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 34.472m 490.798ms 22 50 44.00
V3 TOTAL 22 50 44.00
TOTAL 942 970 97.11

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results