GPIO Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.510s 88.673us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.490s 228.860us 50 50 100.00
gpio_smoke_en_cdc_prim 1.640s 157.952us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.560s 290.645us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 114.801us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.720s 15.282us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.380s 1.339ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.880s 63.605us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.860s 42.485us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.720s 15.282us 20 20 100.00
gpio_csr_aliasing 0.880s 63.605us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.320s 135.066us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.400s 141.942us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.010s 57.928us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.550s 232.117us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.500s 1.247ms 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.650s 376.401us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.570s 3.067ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.920s 594.991us 50 50 100.00
V2 full_random gpio_full_random 1.100s 86.701us 50 50 100.00
V2 stress_all gpio_stress_all 3.600m 77.606ms 50 50 100.00
V2 alert_test gpio_alert_test 0.610s 66.655us 50 50 100.00
V2 intr_test gpio_intr_test 0.720s 16.404us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.310s 161.089us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.310s 161.089us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.720s 15.282us 20 20 100.00
gpio_same_csr_outstanding 0.880s 20.284us 20 20 100.00
gpio_csr_aliasing 0.880s 63.605us 5 5 100.00
gpio_csr_hw_reset 0.690s 114.801us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.720s 15.282us 20 20 100.00
gpio_same_csr_outstanding 0.880s 20.284us 20 20 100.00
gpio_csr_aliasing 0.880s 63.605us 5 5 100.00
gpio_csr_hw_reset 0.690s 114.801us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.560s 416.037us 20 20 100.00
gpio_sec_cm 1.160s 321.779us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.560s 416.037us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 5.042m 8.061ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 940 970 96.91

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results