GPIO Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.560s	56.844us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	91.969us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.470s	892.463us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	491.846us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	161.216us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.630s	15.120us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.190s	262.324us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	76.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.750s	146.985us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.630s	15.120us	20	20	100.00
		gpio_csr_aliasing	0.870s	76.251us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.500s	951.567us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.350s	254.862us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.970s	166.392us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.650s	109.329us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.920s	472.969us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.860s	94.403us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.210s	2.086ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.330s	7.310ms	50	50	100.00
V2	full_random	gpio_full_random	1.160s	367.326us	50	50	100.00
V2	stress_all	gpio_stress_all	3.897m	16.974ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	23.611us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	28.702us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.380s	162.403us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.380s	162.403us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.630s	15.120us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	38.077us	20	20	100.00
		gpio_csr_aliasing	0.870s	76.251us	5	5	100.00
		gpio_csr_hw_reset	0.690s	161.216us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.630s	15.120us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	38.077us	20	20	100.00
		gpio_csr_aliasing	0.870s	76.251us	5	5	100.00
		gpio_csr_hw_reset	0.690s	161.216us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	132.593us	20	20	100.00
		gpio_sec_cm	0.970s	83.502us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	132.593us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.305m	11.644ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			937	970	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test gpio_stress_all_with_rand_reset has 33 failures.
  - 1.gpio_stress_all_with_rand_reset.13311299122475020879019128808766928558350947028343230402825427130317608694677
    Line 462, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1350358720 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1350358720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.gpio_stress_all_with_rand_reset.81989541180240145019489181043139308636619353018832513020364767242580096870115
    Line 584, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2167124293 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2167124293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

GPIO Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `098010d125`