GPIO Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	329.438us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	399.782us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.460s	165.819us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.470s	103.070us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.630s	50.897us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	36.796us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.250s	253.337us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	32.111us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.560s	311.765us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	36.796us	20	20	100.00
		gpio_csr_aliasing	0.850s	32.111us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.280s	221.762us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.330s	69.702us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.940s	46.531us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	94.208us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.540s	118.596us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.550s	362.844us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.100s	1.674ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.450s	1.986ms	50	50	100.00
V2	full_random	gpio_full_random	1.070s	162.741us	50	50	100.00
V2	stress_all	gpio_stress_all	3.486m	15.866ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	12.540us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	184.381us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.260s	208.045us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.260s	208.045us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	36.796us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	74.885us	20	20	100.00
		gpio_csr_aliasing	0.850s	32.111us	5	5	100.00
		gpio_csr_hw_reset	0.630s	50.897us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	36.796us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	74.885us	20	20	100.00
		gpio_csr_aliasing	0.850s	32.111us	5	5	100.00
		gpio_csr_hw_reset	0.630s	50.897us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.440s	516.010us	20	20	100.00
		gpio_sec_cm	0.930s	146.979us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.440s	516.010us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	4.539m	38.173ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test gpio_stress_all_with_rand_reset has 32 failures.
  - 0.gpio_stress_all_with_rand_reset.7747966931935355715358112336745373682786810525837401584791607283603292471746
    Line 537, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 307136535 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 307136535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.56436741261724382514001135285238753612109064182980812055214897372758660917159
    Line 307, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 142072536 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 142072536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.

GPIO Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `584c3d46af`