GPIO Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.560s 242.567us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.470s 95.432us 50 50 100.00
gpio_smoke_en_cdc_prim 1.520s 889.707us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.450s 70.204us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 34.412us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 38.170us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.190s 251.733us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.840s 99.639us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.470s 117.496us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 38.170us 20 20 100.00
gpio_csr_aliasing 0.840s 99.639us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.420s 267.276us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.410s 232.340us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.980s 31.188us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.530s 102.225us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.520s 1.162ms 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.830s 88.457us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.470s 2.862ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.230s 387.903us 50 50 100.00
V2 full_random gpio_full_random 1.100s 387.071us 50 50 100.00
V2 stress_all gpio_stress_all 3.808m 16.811ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 39.374us 50 50 100.00
V2 intr_test gpio_intr_test 0.650s 53.783us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.950s 607.128us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.950s 607.128us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 38.170us 20 20 100.00
gpio_same_csr_outstanding 0.890s 153.190us 20 20 100.00
gpio_csr_aliasing 0.840s 99.639us 5 5 100.00
gpio_csr_hw_reset 0.690s 34.412us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 38.170us 20 20 100.00
gpio_same_csr_outstanding 0.890s 153.190us 20 20 100.00
gpio_csr_aliasing 0.840s 99.639us 5 5 100.00
gpio_csr_hw_reset 0.690s 34.412us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.460s 126.020us 20 20 100.00
gpio_sec_cm 0.980s 617.696us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.460s 126.020us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 4.635m 18.227ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 940 970 96.91

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results