GPIO Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.480s 1.139ms 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.470s 160.867us 50 50 100.00
gpio_smoke_en_cdc_prim 1.560s 675.352us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.550s 345.523us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 17.754us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.670s 16.427us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.430s 1.496ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.890s 150.411us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.670s 33.712us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.670s 16.427us 20 20 100.00
gpio_csr_aliasing 0.890s 150.411us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.360s 219.112us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.340s 35.844us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.970s 473.581us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.410s 439.932us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.750s 921.633us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.310s 338.251us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 28.490s 3.334ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.210s 760.045us 50 50 100.00
V2 full_random gpio_full_random 1.160s 87.966us 50 50 100.00
V2 stress_all gpio_stress_all 3.452m 18.515ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 37.304us 50 50 100.00
V2 intr_test gpio_intr_test 0.680s 17.230us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.820s 274.280us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.820s 274.280us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.670s 16.427us 20 20 100.00
gpio_same_csr_outstanding 0.950s 74.401us 20 20 100.00
gpio_csr_aliasing 0.890s 150.411us 5 5 100.00
gpio_csr_hw_reset 0.690s 17.754us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.670s 16.427us 20 20 100.00
gpio_same_csr_outstanding 0.950s 74.401us 20 20 100.00
gpio_csr_aliasing 0.890s 150.411us 5 5 100.00
gpio_csr_hw_reset 0.690s 17.754us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.620s 720.960us 20 20 100.00
gpio_sec_cm 0.990s 387.215us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.620s 720.960us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 4.037m 23.957ms 16 50 32.00
V3 TOTAL 16 50 32.00
TOTAL 936 970 96.49

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results