GPIO Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	83.663us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.520s	160.729us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.450s	221.925us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.490s	315.455us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	28.107us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.750s	45.912us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.280s	378.365us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	37.162us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.450s	110.651us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.750s	45.912us	20	20	100.00
		gpio_csr_aliasing	0.890s	37.162us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.310s	160.425us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.340s	651.467us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.070s	674.867us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	120.153us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.400s	246.046us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.630s	88.161us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	30.500s	3.734ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.680s	1.096ms	50	50	100.00
V2	full_random	gpio_full_random	1.040s	97.674us	50	50	100.00
V2	stress_all	gpio_stress_all	3.082m	17.821ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.610s	15.368us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	26.073us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.930s	142.693us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.930s	142.693us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.750s	45.912us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	21.377us	20	20	100.00
		gpio_csr_aliasing	0.890s	37.162us	5	5	100.00
		gpio_csr_hw_reset	0.690s	28.107us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.750s	45.912us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	21.377us	20	20	100.00
		gpio_csr_aliasing	0.890s	37.162us	5	5	100.00
		gpio_csr_hw_reset	0.690s	28.107us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	615.911us	20	20	100.00
		gpio_sec_cm	0.880s	577.539us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	615.911us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	4.567m	119.409ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test gpio_stress_all_with_rand_reset has 29 failures.
  - 0.gpio_stress_all_with_rand_reset.13667657233753776832476620341805062318275130466110928663766008297140783398167
    Line 318, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 198182032 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 198182032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.88601373369122734464471515621164440247881359346588464210977570069878798252652
    Line 331, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 443669603 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 443669603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

GPIO Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f1535c5540`