GPIO Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.630s	297.854us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.490s	162.412us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.410s	87.104us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.610s	651.502us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	69.722us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	41.677us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.960s	79.464us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	35.613us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.610s	60.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	41.677us	20	20	100.00
		gpio_csr_aliasing	0.860s	35.613us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.460s	234.201us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.420s	68.634us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.970s	102.523us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.630s	106.791us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.670s	154.274us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.820s	99.714us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.610s	1.989ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.730s	2.077ms	50	50	100.00
V2	full_random	gpio_full_random	1.230s	206.433us	50	50	100.00
V2	stress_all	gpio_stress_all	3.881m	40.690ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	12.748us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	14.212us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.210s	586.498us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.210s	586.498us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	41.677us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	43.135us	20	20	100.00
		gpio_csr_aliasing	0.860s	35.613us	5	5	100.00
		gpio_csr_hw_reset	0.660s	69.722us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	41.677us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	43.135us	20	20	100.00
		gpio_csr_aliasing	0.860s	35.613us	5	5	100.00
		gpio_csr_hw_reset	0.660s	69.722us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.440s	423.163us	20	20	100.00
		gpio_sec_cm	0.970s	2.151ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.440s	423.163us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	5.208m	8.192ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			945	970	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test gpio_stress_all_with_rand_reset has 25 failures.

    • 1.gpio_stress_all_with_rand_reset.115491685024241814181120150672902629449099909665768103077528888941737343548211
      Line 726, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11308702899 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11308702899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.109769252557062671016530393897919568977397451689134076212729216847131693318203
      Line 553, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 872908253 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 872908253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

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