GPIO Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.860s 170.108us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.770s 67.947us 50 50 100.00
gpio_smoke_en_cdc_prim 1.680s 831.785us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.350s 181.099us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.870s 106.547us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.760s 17.418us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 2.530s 1.078ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.970s 30.650us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 41.870s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.760s 17.418us 20 20 100.00
gpio_csr_aliasing 0.970s 30.650us 5 5 100.00
V1 TOTAL 254 255 99.61
V2 direct_and_masked_out gpio_random_dout_din 1.760s 1.463ms 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.850s 117.034us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.300s 49.560us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.870s 79.677us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 4.690s 108.049us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 4.130s 778.621us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 26.030s 527.539us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 8.710s 3.095ms 50 50 100.00
V2 full_random gpio_full_random 1.400s 305.833us 50 50 100.00
V2 stress_all gpio_stress_all 3.253m 15.605ms 50 50 100.00
V2 alert_test gpio_alert_test 41.521s 49 50 98.00
V2 intr_test gpio_intr_test 0.850s 40.423us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 41.791s 19 20 95.00
V2 tl_d_illegal_access gpio_tl_errors 41.791s 19 20 95.00
V2 tl_d_outstanding_access gpio_csr_rw 0.760s 17.418us 20 20 100.00
gpio_same_csr_outstanding 41.903s 19 20 95.00
gpio_csr_aliasing 0.970s 30.650us 5 5 100.00
gpio_csr_hw_reset 0.870s 106.547us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.760s 17.418us 20 20 100.00
gpio_same_csr_outstanding 41.903s 19 20 95.00
gpio_csr_aliasing 0.970s 30.650us 5 5 100.00
gpio_csr_hw_reset 0.870s 106.547us 5 5 100.00
V2 TOTAL 637 640 99.53
V2S tl_intg_err gpio_tl_intg_err 41.837s 19 20 95.00
gpio_sec_cm 1.200s 144.256us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 41.837s 19 20 95.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 3.563m 12.513ms 17 50 34.00
V3 TOTAL 17 50 34.00
TOTAL 932 970 96.08

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 14 14 11 78.57
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results